Computing devices (e.g., servers, desktop or laptop personal computers, tablet computers, smartphones, portable game consoles, etc.) and other electronic components and devices may include one or more processors for accessing a memory that is electrically coupled to a memory controller via a bus. The processing power and memory performance of such devices continue to increase to meet consumer and industrial demands. It may be desirable to use memory that offers the highest possible performance in devices and applications such as, servers, graphics engines, networking processors, search processors, defense electronics, and automotive electronics. However, as memory bandwidth increases, variations in memory temperature can become more problematic and negatively impact the intended performance and operation of the memory.
For example, in existing dynamic random access memory (DRAM) interfaces, such as, Low Power Double Data Rate (LPDDR), Graphics Double Data Rate (GPDDR), High Bandwidth Memory (HBM), Hybrid Memory Cube (HMB), etc., bus timing parameters may be adversely impacted by temperature variations. High-performance DRAM interfaces must handle extremely small tolerances in their timing budget in order to achieve increased signaling rates. Current DRAM supports external interfaces that can communicate with, for example, a system on chip (SoC) at speeds up to and exceeding 7 Gigabytes per second (Gbs). One example of a critical DRAM timing parameter subject to temperature variation is the timing path between the DRAM internal clock strobe and the data bus input/output (I/O) pins (referred to in the art as “DQ” pins). This timing path originates from a DQ strobe receiver pin (referred to in the art as a “DQS” pin) and then fans out to each of the DQ pins. Even relatively small temperature variations in the DRAM can alter the delay of the DQS signal along this timing path, which directly influences the speed of communications between the SoC and the DRAM bus. This is because the rising and falling edges of the DQS signal are used to sample the DQ signals, and DQS edges should ideally be aligned with the center (in-between signal transitions) of each DQ bit to ensure that DQ is stable and has the correct (logic high or logic low) voltage when it is sampled. Changes in the delay of DQS can result in DQ being sampled too early or too late (i.e. offset from the ideal center point) during which DQ may be unstable or may not be at a proper voltage.
Existing solutions for addressing DRAM temperature drift are limited. For lower frequencies (e.g., under 2 Gbs), DRAM temperature variation may be handled by over-designing or over-margining the SoC-to-DRAM interface such that any value of temperature drift will not violate any timing. As frequencies increase, however, it may not be possible to over-design the system. Therefore, the DRAM temperature drift must be periodically measured and, if the timing drift of DQS exceeds a threshold, timing recalibration must be performed. During recalibration, the system measures the amount of DQS temperature drift and then compensates by inserting or removing time delay on the DQS signal using programmable delay circuits within the SoC. Depending on the workload, the system temperature and the DRAM temperature may rise and fall, which leads to temperature-induced timing drift. If left uncorrected, the timing drift may result in bit errors on the interface. Furthermore, there is a performance penalty when resolving timing drift in this manner. Periodic recalibration places the DRAM offline during which the DRAM data cannot be accessed, thereby reducing memory performance. These problems will only be exacerbated as memory speeds continue to increase.
Accordingly, there is a need for improved systems and methods for managing memory temperature variations, which can negatively impact the performance and operation of memory, such as, DRAM.